I'm designing the logic for a project with very slow memory. My question is about the behaviour of the PowerPC data cache in V4FX, when writing to memory.
In the PPC block datasheet pg 72 is said, that the PLB DCU cannot pipeline multiple write requests. I imagine the following situation:
- store-without-allocate is set (no allocation)
- PPC software writes to memory location A (cache miss)
- DCU starts PLB write cycle A
- PLB slave receives data and acks to the master
- PLB slave initiates (slow) memory access in the background
- PPC software writes to memory location B (cache miss)
- DCU starts PLB write cycle B
- PLB slave is not ready, acks address but can't accept data.
- PPC software writes to memory location C (cache hit)
Does the PPC reach step 9 immediately, although the DCU is being blocked in step 8?
If yes, does the PPC immediately finish step 9 (recognizing that wait for DCU is not necessary)?
Kind regards, Marc