Field-Programmable Gate Arrays

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1.8V config proms for Cyclone 2s

Hi folks, Is it possible to get EPROMs for Altera (Cyclone 2) devices that work at 1.8V? I appreciate the help and insig...
0 comments posted 19yrs
posted by fpgabuilder-groups
0 comments posted 19yrs posted by fpgabuilder-groups

FF's are inffered instead of distributed RAM

i have a byte array of size 10 and i need to shift values in the array to left by 5 positions in 5 clocks. here is the...
2 comments posted 19yrs
posted by manusha
2 comments posted 19yrs posted by manusha

Using xilkernel with C++

Hi, is there a way to get the Xilkernel to run with a C++ application? I didn't find any option for this in the XPS "So...
2 comments posted 19yrs
posted by Guy.Eschemann
2 comments posted 19yrs posted by Guy.Eschemann

FPGA with 5V and PLCC package

We use in a laboratory course still XILINX XC3000 FPGAs with Viewlogic's Workview design entry (DOS version) and XILINX...
44 comments posted 19yrs
posted by klee
44 comments posted 19yrs posted by klee

prog_b held low?

working with a custom board with a V4 on it. It has been working fine for a couple of months until last week - when the...
3 comments posted 19yrs
posted by mtsukanov
3 comments posted 19yrs posted by mtsukanov

timing in xilinx fpga

Hello everybody, I am using Xilinx Timing Analyzer in order to see average delay per each wire type, i.e. for double, h...
8 comments posted 19yrs
posted by ruzica
8 comments posted 19yrs posted by ruzica

create test bench of video

hi every body , i m asked to read a video using an FPGA , can you please give me some ways that let me adopt to create...
2 comments posted 19yrs
posted by abaidik
2 comments posted 19yrs posted by abaidik

Xilinx ISE Inferred block rams

I am getting a warning on 18 and 36 bit wide block rams inferred in my Verilog code in ISE 9.1. The following code is a...
4 comments posted 19yrs
posted by harmon.darrell
4 comments posted 19yrs posted by harmon.darrell

Sparten 3E clock generator

What is the best way to generate a 125Khz square wave? The DCM only goes down to 5Mhz. Thanks.
1 comments posted 19yrs
posted by tdashmike
1 comments posted 19yrs posted by tdashmike

ModelSim PE exit code 211

When I try to run a timing simulation (simprim is used) modelsim pe student exits with fatal error and exit code 211. M...
2 comments posted 19yrs
posted by outofmem
2 comments posted 19yrs posted by outofmem

Altera introduces Cyclone III devices, ships 65nm

Hello: Today, Altera announced the Cyclone III device family. Highlights: Industry's first 65nm low cost FPGA Shipping...
27 comments posted 19yrs
posted by lschirrm
27 comments posted 19yrs posted by lschirrm

a project work

hi all i am an engineering final year student in english i am doing a project on "CONFIGURING FPGA USING XC9500 CPLD AN...
2 comments posted 19yrs
posted by jaggunitj
2 comments posted 19yrs posted by jaggunitj

alliance tooset on Linux

I'm trying to install the alliance toolset on an Ubuntu linux machine. I've downloaded both a tarball and RPM sources....
1 comments posted 19yrs
posted by lyttlec
1 comments posted 19yrs posted by lyttlec