a project work

Use the Xilinx tools for an FPGA design to produce the .bit file in the "Generate Programming File" step in the Xilinx ISE GUI.

"Generate PROM, ACE, or JTAG file" (under "Generate Programming File" in the GUI) to launch and use the Xilinx Impact utility.

Read the "Configuration" section in the data sheet for the part you're going to program.

You need to learn how to use VHDL on your own. "how to use assembly language" might be an equivalent question. It's the language used to describe the functionality of the part. As far as the role: you can use VHDL to describe the functionality of your CPLD and to design the FPGA that you'll be generating the bitstream for.

Do you know anything about VHDL? If you're taking this on as a project, you should have certain prerequisites, one of which is certainly the use of RTL languages in hardware design.

You definately need to start with simple VHDL/Verilog program, like blinky LED, synthesize the code and download bitstream into FPGA for testing. This will give you at least basic idea of the design flow.

Check

Although new Spartan3E family is capabale of self-configuring from parallel flash.

good luck!