Spartan 3A Starter Kit Multiboot Demo Config 4 Display Problem

Hi, My name is Bryan from Xilinx Asia Pacific. I have on hand a Spartan 3A Starter Kit . However, I was trying out Multiboot Demo Config option 4 which is a video pass through demo that does not seem to work out though. I hook up a camera through a composite cable to a video decoder peripheral which is connected to the starter kit via J17 connector. In addition a LCD monitor is also connected via VGA port to the Starter Kit. No image appears on the monitor when config 4 was run. I thought I was supposed to see images captured by the camera on the LCD. Can anyone help me with this?

Also I would like to ask is it possible to port a design within the Spartan

3A Starter Kit PROM to another Spartan 3A Starter Kit PROM. If it is possible, what are the steps needed to be done?

Thank you

Reply to
Bryan
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Dear Bryan,

can you please tell us where you have found ANY reference that the S3astarter demo designs support video input from J17?

maybe those demos are available for Xilinx employees, but from Xilinx public website I see no such demos, or any reference to any video input designs for s3a starterkit board.

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there are only video demos that take text and images either from BRAM of NOR Flash, there are absolutly NO DEMOS that use DDR2 memory on the s3a starterkit.

Antti

Reply to
Antti

Hi Bryan,

The Spartan-3A Starter Kit, as shipped, does not include a "video pass through" demo. The main demo does allow you to MultiBoot to other designs in the flash, and there is a "configuration 4" but that design is actually Ken Chapman's parallel flash programmer design.

Now, it does happen to be the case that other designs exist, but they are not (yet) posted. One of them is a video pass through design, where you connect a Digilent VDEC1 board to J17, and apply a composite video signal. The video is decoded on that expansion board, then color space converted and line doubled for output on the VGA port. In addition, there is a provision to use an attached mouse to draw on the live video (a monochrome, bitmapped overlay) and load/save overlay bitmaps into the flash. There is another derivative design, scheduled for release with the Spartan-3AN Starter Kit, that omits the video decoding, resulting in a design that is much like the Microsoft Windows "Paint" accessory...

Maybe you saw the video pass through design at an XFEST event or at the Spartan-3AN press release event? Otherwise, I am not sure how you would know it exists. If you are looking for that design, please contact your local FAE or sales representative for assistance. I am not sure if/when this design will be posted.

As for the derived "paint" design, that will be available when the Spartan-3AN Starter Kit is released. This specific design only works on Spartan-3AN as it leverages the internal flash for storing the bitmaps.

Regarding your final question, I am not sure I understood what you are asking. I encourage you to file a support case with the Xilinx customer support team to receive official support for your product.

Hope that helps, Eric

Reply to
Eric Crabill

:) Err.., I think he IS the local FAE / Sales rep, as his address claims Xilinx ?.

It maybe that it was an 'oops' posting, meant to go upstream inside Xilinx. [yes, does happen sometimes...]

Any comments/release schedules re Antti's questions about DDR2 working examples on 3A demo system ?

-jg

Reply to
Jim Granville

Hi Jim,

I don't usually look at the message headers, because it plays no role in my deciding to answer a question. Maybe Bryan does work with/for Xilinx! In any case, Bryan, I hope I answered your question.

You can get a working DDR2 interface from MIG 1.7 specifically for the Spartan-3A Starter Kit. There's also a working design derived from that in the board test design that is posted on the Spartan-3A Starter Kit reference design page. I think what some previous posters wanted was more than "working", rather a "stress test" or something that really demonstrates the bandwidth of the memory interface. I agree that such a demo or reference design would have value. Do I have any comments/release schedules to share? No, sorry.

Eric

Reply to
Eric Crabill

Eric Crabill schrieb:

Eric,

it looks like I am missing something :(

1) the only thing at X-Fest was the rotazoom that takes images from NOR flash no video pass through demo (at X-Fest in Munich)

2) the only "derived" DDR2 design seems to be board test design where PicoBlaze reads out the MIG testbench error led status and displays p or f on hyperterminal - is this the MIG derived design you have been referreing to, or is there some more functional design available?

Antti

Reply to
Antti

Hi all, sorry for the confusion, anyway to answer any doubts, the said demo was the one as described by Eric Crabill where you can edit the picture from the camera on the video display. The hardware used is also as described by Eric. This design i am not sure why is it not posted yet. Well i do work in Xilinx Asia Pacific and i have posted internal tech support as well but no reply yet. Also I did not see this demo at XFEST , rather tomorrow is XFEST @ Singapore and I am manning the booth, so that is why i sound so troubled and urgent. Meanwhile i have contacted faes and sales rep as well so hopefully it will all work out.

(P.S: I am not that well versed in FPGA system level design yet, just a newbie)

Reply to
Bryan

Yes.

Reply to
Eric Crabill

Hi

dont worry so much - when I was at X-Fest munich then the first question I asked at Spartan-3A booth: "may i see the DNA demo?" caused the support personal to seek for printed documents and reading them (means they had not done their homework).

While seeing the S3A board first time I figured out the way to start the DNA demo before the support personel found it the printed documents.

So it is good that you are trying todo your homework ahead of time, it may avoid trouble with difficult questions at the booth. I hope that you do not get trouble asking a "xilinx internal support question" at public newsgroups, as in many times c.a.f. can deliver results WAY faster then Xilinx WebCase.

sidenote to Xilinx: there is room for improvment for information flow within Xilinx? (To improve the ability of Xilinx employees to support Xilinx customers)

Antti

Reply to
Antti

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