Answer: maximum number of state machines in a current chip: > 500k

Sep 22, 2007 6 Replies
W

Hi, Here is the answer to the maximum number of state machines in a current chip: > 500k.



My original answer posing has some errors.


  1. It is L2 cache that uses a lot of state machines;
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  1. IBM/Intel uses MESI protocol (4 states: Modified, Exclusive, Shared and Invalid);
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  2. Please visit Intel product website to get the latest news:
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  1. "with up to 8 MB of L2 cache per processor" and 4 processors. It means 4*8MB = 32MB L2 cache;

  2. L2 cache is divided into data L2 cache and instruction L2 cache and only data L2 cache uses MESI protocol.


  1. Each 32Bytes is a cache line;

  2. 32MB/2/32 = 500k cache lines in data L2 cache and 500k state machines using MESI protocol.


  1. L1/L3 cache and instruction L2 cache use several independent 1-bit flip-flops to recode their states so that they are not counted as state machines.



The final answer is: There is at least 500k state machines in Intel chip.



a. It is available to every users in the topics groups; b. They are written in Verilog, not in VHDL; c. FPGA has never had a design using L2 cache.



Weng



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J

Likewise, the mediaeval discussions about how many angels can dance on the head of a pin are accessible to all. In both cases, most of us don't care.

Utterly unimportant, and possibly not even true. Intel uses a range of proprietary in-house tools and languages in addition to Verilog.

Even if that is true, I defy you to prove it.

Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
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J

Which leads us to another interesting question ....

What are the maximium number of lemons that the human mind can imagine being rotated simultaneously?

[Please note the lemons can not be bruised. This is a degenerate case that the theorem does not apply]

-- Regards, John Retta Owner and Designer Retta Technical Consulting Inc.

email : snipped-for-privacy@rtc-inc.com web :

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E

Why? Wouldn't the smart thing be to build *one* cache coherency controller in your chip, and to save your 2 state bits as two extra bits in the 256 memory bits in your cache block?

Actually, to the religiously inclined (among whose number I am not, alas, to be counted) this is potentially a very interesting question. The debate was actually about whether or not Angels had a corporeal existence; the title was just whimsy. Thomas Aquinas's answer, for the case of a pinhead which was a geometrical point, was, I think, 'one'.

So, maybe there was something fundamental we missed in the original question. Was it just an allegory? One FSM, one Angel. Spooky.

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N

And there is also one more big error.

news:

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If you read the product brief again, you should see that there is only

8MB of L2 on the whole chip. This is split into 2 sets of 4MB which can then be accessed by 2 cores. Where Intel says processor they are referring to the whole chip, and core is used to refer to the 4 processors on the chip.
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M

saying that there are more than 500K state machines has not stated what the maximum number can be.

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G

It all depends on how you look at it; from a certain point of view, the correct answer is one (1).

What you are calling state machines are just subordinate pieces of one grand state machine.

G.

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