ANNOUNCE: Embedded hw/sw developer freebies by Nikolaos Kavvadias

Hello fellow developers, users and friends

This is a list of free (some of them GPL'ed) tools that I have written over the course of the few last years. You can access and download the tools from:

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Everyone is welcome to comment on the tools by posting to this thread or via email.

Enjoy Nikolaos Kavvadias Computer Architecture Developer and Compiler Specialist Ph.D. candidate

====================================================== = List of architecture, compiler, and hardware tools = ======================================================

  1. A data-dependence graph construction pass for the Machine-SUIF research compiler infrastructure, called bbpart. It generates a textual representation for the data dependence graphs of the basic blocks found in all the procedures of a given ANSI C source file. There is also an older version that generates a visual representation in the VCG format for each DDG.

  1. SUIFvm instruction set support for the CDIF (Connected Dataflow Idiom Finder) instruction generation tool.

  2. A patch for the OLIVE code generator-generator tool, currently only available as part of the SPAM research compiler, which is built on top of SUIF 1.

  1. Instruction-accurate ArchC model for the (integer ISA) DLX processor.

  2. A patch applying modifications to archc-2.0beta2 so that it can compile with a gcc-2.x-based compiler.

  1. An implementation of a hardware looping unit (HWLU) in VHDL had been posted to OpenCores around April 2004. The HWLU can be used for developing non-programmable engines for multi-dimensional signal processing algorithms that are comprised of fully nested loops. It is accompanied by software tools for generating parts of the VHDL description of the hardware.

There is also a couple of specialized compiler passes related to zero- overhead loop control (ZOLC) in embedded programmable processors.

  1. tcfggen is an analysis pass built to be used with the SUIF2/ MachSUIF2 compiler infrastructure. tcfggen performs (natural) loop analysis in order to map the control flow of a given optimization unit (i.e. a procedure in the input program) to its task control flow graph (TCFG). It is also used to pass the static information for the loops in the given procedure to the subsequent stage(s) in the form of pseudo-instructions.

  1. zolcgen is a transformation pass operating on SUIFrm assembly files, utilizing the SALTO (System for Assembly Language Transformation and Optimization) API. This pass produces the actual ZOLC initialization code that has to be inserted in a preceding basic block to the loop nest to update the ZOLC storage resources and is typically the first basic block of the targeted procedure.

  2. Kernel benchmarks for evaluating the ZOLC optimizations.
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