I use a design in which I have detected some skew problems. I have seen the archive.ucf (with the constraints), so "slew" and "drive" properties are used in some pins. I suppose that these properties are used for delays, but I don't know for what.
Can anyone explain me the meaning of these properties?
For LVCMOS and LVTTL outputs, there are selectable drive strengths ans slew rates (Xilinx parts). SLEW=SLOW or SLEW=FAST select the two possible output slew rates. Unconstrained LVTTL and LVCMOS outputs default to SLEW=SLOW to reduce ground bounce and noise.
DRIVE=n, where n is the strength in milliamperes, defines the drive strength. For most outputs the default frive is 12 mA. Available strengths depend on the I/O standard used.
In the electrical specifications for your part, there are tables of timing adders for the various output standards, drive strengths and slew rates. It is possible to address skew issues between source-synchronous pins by assigning differing SLEW or DRIVE properties, but it's probably a Band-Aid approach to fixing a problem. Usually, at least in the recent parts containing DCM's, it's better to handle timing shifts with clock phase shifting, or in the newest parts using variable delay elements in the IOB's.
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