Field-Programmable Gate Arrays

Xilinx XChecker cable supported until which version?

Hi I have Xilinx ISE 7.1 and wanted to use the Xilinx XChecker cable to connect to the JTAG interface. Unfortuantely th...

1 comments posted 18yrs

posted by Florian

1 comments posted 18yrs posted by Florian

how to generate a linker script?

Hello all, i am trying to find how to generate a linker script in edk 6.2 ver. I googled it but i dint find something he...

0 comments posted 18yrs

posted by lastval

0 comments posted 18yrs posted by lastval

Bidirectional open drain port

Dear all, I guess Bidirectional open drain port can be implemented in FPGA...From the data sheet i understood that it c...

0 comments posted 18yrs

posted by fazulu.vlsi

0 comments posted 18yrs posted by fazulu.vlsi

scanf and printf in EDK's BSP

I am working on a PPC405 system using EDK9.2 and its BSP. The system uses an uartlite as stdin and stdout. I am unable...

6 comments posted 18yrs

posted by rha_x

6 comments posted 18yrs posted by rha_x

Spare Spartan3's

Hi, I've got some spare Spartan3-200's (XC3S200TQ144) which are left over from a project. I have ~40 non-RoHS compliant...

0 comments posted 18yrs

posted by dave.bryan

0 comments posted 18yrs posted by dave.bryan

ISE and Itanium

Hi everybody! Is Itanium supported by ISE software? Best Regards

1 comments posted 18yrs

posted by taileb.mehdi

1 comments posted 18yrs posted by taileb.mehdi

Hook open drain "power good" to nSTATUS or nCONFIG?

I'm using a Cyclone II with 1.2V core. The 1.2V regulator has an open drain "power good" signal and a cap to delay that...

4 comments posted 18yrs

posted by ben

4 comments posted 18yrs posted by ben

Converting a ByteBlasterMV into a ByteBlaster II?

Argh. I just discovered that my ByteBlaster MV clone can't program an EPCS configuration PROM, but the ByteBlaster II c...

3 comments posted 18yrs

posted by nevo

3 comments posted 18yrs posted by nevo

Xilinx Dual processor design

Hi all I am using Xilinx dual processor reference design suite to develop dual processor (xapp996) system on virtex-2 p...

3 comments posted 18yrs

posted by naresh.hk

3 comments posted 18yrs posted by naresh.hk

Start-up Xilkernel on Microblaze

Hi, How many long Xilkernel take to startup with microblaze (System Clock : 50 MHz). On my design, the Microblaze need...

2 comments posted 18yrs

posted by yannick.deal

2 comments posted 18yrs posted by yannick.deal

using fpga as programmable connection

hi, i would like to use a small fpga (or cpld) on a pcb to make direct bidirectional connections between pins. basicall...

5 comments posted 18yrs

posted by nospam

5 comments posted 18yrs posted by nospam

Fifo Block-RAM Xilinx ISE - port empty

Hello, I have generated a block-ram based FIFO queue (2 independent clocks, 2 inputs, 1 output) with the use of Core Ge...

0 comments posted 18yrs

posted by paraliczb

0 comments posted 18yrs posted by paraliczb

vhdl state machine

I have a following state machine. enable is an input comiing from a accumulate core. Now the total number of inputs to...

2 comments posted 18yrs

posted by nbg2006

2 comments posted 18yrs posted by nbg2006

How to simulate these example CORDIC code?

Hi, I want to learn the implementation of CORDIC. I find the following website has some code which I would like begin w...

13 comments posted 18yrs

posted by rxjwg98

13 comments posted 18yrs posted by rxjwg98

can't read/load memory contents

Hello there, one of new members around here. I've got a problem while i try to retrieve/pass over some values to memory...

7 comments posted 18yrs

posted by dartanians

7 comments posted 18yrs posted by dartanians