VCCIO issue on Xilinx Spartan3E !

I forgot to tell that these conditions comes before downloading the FPGA just after the power-on of the board with stable Power Supply.

I forgot to tell that these conditions comes before downloading the FPGA just after the power-on of the board with stable Power Supply.

Larry,

The FPGA is not a battery. If there is that high a voltage on unconnected banks, well, they are obviously connected to something, aren't they?

It could be that you have a 5V CMOS driver driving an input in that (those) bank(s), which causes the upper protection diode(s) to be forward biased.

The voltages you have reported are greater than the abs max in the data sheet, so you risk blowing out the gates/junctions on the IO transistors in those banks -- DON'T DO THAT!

Austin

I don't think the chip cannot manufacture voltages, so you need some simple tests

• Check the voltmeter is correct

• Find any higher voltages on the board - it is really is correct it must be coming from somewhere else.

That's also quite a low impedance, you have pulled 24mA from the pin, and only dropped 600mV

-jg

Austin,

Yes, you saw the correct trouble : FORWARD BIASE.

But how? An pin on a connector can output io signal coming from Bank1 or can drive a regulated 5V. The selection of these two output are done with a analog FET switch. BUT, the pull-down resistor setting the Switch was 470k instead the 4k7 ;-)... Before the configuration of the FPGA, the 5V was coming on one io of bank1 then via the protection diode the

5V comes on all the VCCIO of bank1 and Bank3... Note: after configuration of the SP3 all comes correct since the FPGA drives the analog switch :-)

The Spartan3E was stressed, but still working !

Thank you Austin.

Regards, Larry