Resource utilization broken down by hierarchy?

Question

Hello,I am interested in looking at the resource utilization of a design Iam working on broken down based on the RTL hierarchy of the design.  Iam using a Virtex-II Pro part.  I have seen in the past where you cando this using Floorplanner, however when I attempt to use Floorplanneron my design I get the following error...."The design contains macros with RPM grid coordinates which are notsupported by Floorplanner"After digging a little in Xilinx's Answer Database, I don't believethat there is a way around this based on this answer....Specifically, this line....NOTE: These solutions will not work if any of the cores have hardwaremultipliers because the RPM_GRID system must be used with multipliers.I use hardware multipliers in my design.Does anybody have any ideas as to how I could get my design infloorplanner, or another option for viewing the broken down resourceutilization?Thanks for all the help.Regards,John

Barry · Accepted Answer

I use a program called Adept for this.

paragon.john · Answer

Thank looks promising, except I am using ISE 8.2 and it looks likeAdept only supports 9.1 and 9.2.  Any other ideas?Thanks.

Martin Thompson · Answer

You could try FPGAOptim  - it'sdesigned for just such a job (Full disclosure - I wrote it :-)Please mail me if you want a copy.  It allows me to keep track of whoneeds updates (a V5 updates is in the offing...)Cheers,Martin--  TRW Conekt - Consultancy in Engineering, Knowledge and Technology

jtw · Answer

A relatively simple method is to do individual synthesis & ngdbuild/map for your block(s) of interest. Be sure to prevent deletion of unused logic, and you probably won't want IO instances.

You can also use this method to get a reasonable estimate of achievable performance for the block by running through par.

JTW

Resource utilization broken down by hierarchy?

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