HI all,
First , I would like to thank the folks who have helped me to solve my last problem of optimizing my Digital Down Converter design to shrink
400% and fit one Virtex chip. Apparently, all I did was to increase the hardware oversampling of my DAFIR blocks to use less parallel filters which worked like a charm. Thank you.However , I have decided to explore the posibility of using the newer FIR compiler block which uses more DSP48 resources instead of the DAFIR block which may not implement resources that efficiently.
However I encountered error while resource estimating on the postmap option. The error reads"Continuous Sample Times not allowed". And yes , I am using a DDC structure of CIC-CFIR-PFIR filters. The error also seems to point to the Comb part of the CIC filter.
I would appreciate any comments to inspire any solutions. Thank you.