Hi
As mentioned in an earlier post, I need an asynchonous instead of a synchronous data memory. The design was working with the BRAM, but the data was delayed by one cycle. So one would expect when adding a synchronous memory with the right timing behaviour to get the design fully working. So I used the core generator 7.1 and generated a distributed RAM with 1536 words a 32 bits. I used then a .coe file to initialise the content of the distributed RAM cells. I used a black box to map the signals. During translation the RAM is integrated but then when I use Chipscope something strange happens. I have 8 load data from memory instructions, 7 of those transfer the right value but always the third memory access reads a 00000000 into the register. Although cleary I have a value specified in my .ceo... TO be honest I have no clue how to tackle this problem. So I am hoping that maybe someone made the same experience and could tell me a solution for this?
many thanks