Weired Distributed Memory behaviour

Hi

As mentioned in an earlier post, I need an asynchonous instead of a synchronous data memory. The design was working with the BRAM, but the data was delayed by one cycle. So one would expect when adding a synchronous memory with the right timing behaviour to get the design fully working. So I used the core generator 7.1 and generated a distributed RAM with 1536 words a 32 bits. I used then a .coe file to initialise the content of the distributed RAM cells. I used a black box to map the signals. During translation the RAM is integrated but then when I use Chipscope something strange happens. I have 8 load data from memory instructions, 7 of those transfer the right value but always the third memory access reads a 00000000 into the register. Although cleary I have a value specified in my .ceo... TO be honest I have no clue how to tackle this problem. So I am hoping that maybe someone made the same experience and could tell me a solution for this?

many thanks

Reply to
Gerry
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I don't see why this is a problem. An asynch ram has an output delay also. Maybe you need a faster clock. A bird in the hand is worth two in the bush.

Solutions are found by debugging. The standard practice is simulation.

-- Mike Treseler

Reply to
Mike Treseler

Your LUT-RAM-based very big RAM may have long routing delays. If you believe in trying things out (instead of simulation), then reduce the clock rate, and see whether that helps.

Reply to
Peter Alfke

Thanks Peter, you saved my life ;). Reduce clock frequency and now it works which is great news. Anyway, as you suggested I will try and rearrange the logic to make it work with a synchronous BRam

Thanks!

Reply to
Gerry

Hi Gerry, I suggest you make sure you use timing constraints in future. It's all described in the constraints guide. This, used in conjunction with the timing analyser tools, will let you know when things are failing timing. HTH., Syms.

Reply to
Symon

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