'1' or '0' when I/O pin is pulled up

Yes, provided you do all the right things: (1) Make sure that your FPGA doesn't drive SDATA when disabled. (2) Ensure that there is a pullup resistor of appropriate value somewhere on the SDATA bus.

VHDL: port ... SDATA: inout std_logic; ...

--- Park this signal at '1' when you don't want to drive SDATA. signal internal_SDATA_drive: std_logic;

-- Use this signal as input to your SDATA receiver logic: signal internal_SDATA_rcv: std_logic;

... SDATA

Thanks for your detailed explanation!

I assign the SDATA to 'Z' in order to receive data, but the pin is pulled up so I am wondering if the SDATA will read '1' regardless of the actual incoming value.

Nick

J>

Hi Nick,

Nick schrieb:

The simple answer: No, normally the peripheral that puts a '0' on the SDATA line has a driver that is strong enough to pull the line down.

For further investigation: The voltage on your SDATA line can be modeled as a resistor network (in case of high speed or high accuracy a RLC network). This consists mainly of your pullup resistor and the R(DS) of the CMOS transistors in your connected drivers output stage. With these values you can use the formulas for a simple voltage divider to calculate the voltage on your SDATA line.

e.g. Vcc= 3.3V R(pullup) = 1 KOhm R(DSon)= 50 Ohm

V(SDATA) = 3.3V * 50 Ohm/1050 Ohm = 157 mV

which should be read as a '0' on a digital input.

For the actual values in your design take a look in the datasheets of the devices you use. But the example should give you an idea of what is going on when pullups meet drivers.

Have a nice synthesis

Eilert