Hi
lets assume I have two signals, each carrying 8 bits of information. One signal is a so called configuration signal and has exactly 4 bits that are HIGH and 4 bits that are LOW. Now depending on on the values of the configuration signal I wanna reorder the bits in the other signal in the following way: If a bit is set in the configuration signal, then the corresponding bit in the source register will be part of the most significant 4 bits of the result signal. If a bit in the configuration signal is not set then the corresponding bit in the source register will be part of the least significant 4 bits. Difficult to describe, so here an example
Source: A B C D E F G H Configuration: 1 0 1 0 1 0 1 0
Result = ACEG BDFH
So I could have two 8 to 4 - muxes that generate me the 4 MSB bits and 4 LSB bits. Is there maybe a better approach to do implement this on an FPGA?