V4FX: LVCMOS25 vs LVCMOS33 output buffer

Hi all,

Is there a difference which one is instantiated when the actual VCC in the bank is 3.0V?

Thanks, /Mikhail

Reply to
MM
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Hi Mikhail, Compare the bit files? HTH, Syms.

Reply to
Symon

Mikhail,

Only in terms of the number of paralleled output devices selected.

If you wish 8 mA min drive at 2.5v Vcco, the number of drivers will be stronger than that at 3.0, or 3.3 v. Conversely, if 8mA is selected for

3.3v, it will be weaker at 3.0 or 2.5v.

The hspice models on the website will predict actual results from real silicon, whereas the IBIS models do not allow for changing Vcco.

Regardless, simulating 8 mA at 3.3v slow/weak corner in IBIS will give you some idea of what the typical will be with 3.0 volts.

A 10% change in Vcco is roughly the same as the difference from slow/weak to typical, or typical to fast/strong(in IBIS).

Austin

Austin

Reply to
austin

Thanks a lot Austin!

/Mikhail

Reply to
MM

Austin,

Please set up a web-based interface to your (Xilinx) copy of HSPICE for us peons that work for companies that can't or won't purchase their own $100k version of HSPICE.

Thanks in advance, Bob

Reply to
BobW

BobW,

Hspice licenses do not cost 100K, in fact they are >10X less than that amount...

I apologize, but our foundries device models belong to them, and they must remain encrypted, and secret. Hspice is the only vehicle today that is available to support this (and is commonly used to do so).

Are there other spice that support encryption? Sure. But they are not as common as Hspice. We have to support this for all customers, so it isn't for free.

If you submit a webcase, you will get an answer from an IO specialist, if you request a Hspice result for a simulation (or two). Just be SPECIFIC.

And, obviously, the IOB netlist belongs to Xilinx, and we are not interested in disclosing it to the world, so everyone who isn't able to make their 65nm process work, gets a chance to see how we did it.

Austin

Reply to
austin

Austin,

I do understand about the need to protect your property.

It is a frustrating time because edge rates are going beyond what the accuracy of the (low cost) IBIS simulators can provide, and the only other solution is the (high cost) HSPICE stuff.

Here are the approximate HSPICE costs. This includes the license and the simulator front end:

$50K plus $8K/yr (maintenance) or optionally, as a lease: $25K/yr

Bob

Reply to
BobW

BobW,

Hmmm, they have raised their prices since I last checked. Either that, or the people I talk to all fight for a discount.

The cost of one license will still be less than one re-spin and re-manufacture of one pcb assembly lot from one screw-up that the license could prevent (ie it is cheap insurance to get something right the first time).

As to "not understanding about protecting our property" that is something I can not hope to change, as if you do not respect my property rights (or Xilinx' property rights), I would rather not communicate with you any further.

Fine with me.

Have fun.

Enjoy.

Austin

Reply to
austin

Oops.

I thought you did 'not' understand property rights.

I apologize.

My comment on the cost of the license is still valid: it is cheap insurance.

Also, looks like they did raise their prices over what I have been told in years past.

Austin

Reply to
austin

BobW,

Additionally, IBIS is not adequate for MGTs (gigabit transceivers) but perfectly valid for gigabit LVDS (for example).

This has to do with IBIS inability to model the more complex drivers used for the MGTs, not the inability of IBIS and simulators to handle edge rates and t-line effects: they do that just fine.

But, IBIS will not allow you to change the Vcc, as the model was "made" by a particular Vcc, and there is no way to dial in the Vcc you would prefer over the one built into the results (IBIS is just a look-up table, after all).

Austin

Reply to
austin

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