Yet another modelsim problem

Completed process "Generate Post-Translate Simulation Model".

ERROR: Hidden remap failed Reason:

Launching Application for process "Simulate Post-Translate VHDL Model".

not only the software's stupid enough to launch the GUI after the error, but there is not a single entry about this error in the xilinx database, on the modelsim server or even in google (but me complaining about the same problem a month ago) The 'reason' field is as useful as usual :) this time they just didn't bother typing a message that makes no sense, they just left it empty.

here's the code:

process(Reset, MasterClock) is variable counter : std_logic_vector(2 downto 0); begin if(Reset = '1') then counter := "000"; elsif(rising_edge(MasterClock)) then dividedclock

Reply to
Thomas
Loading thread data ...

The FPGAs I have worked and do work with do not allow for a dual edged CLK. Assuming your does and /or assuming the synthesizer does some neat trick to allow this for your FPGA, maybe you could specifiy rising clock edge if in the layer above this entity, you had a faster clock divide by 2 to make this clock that you are using here. I dont' know if that is a possibility, but I do remember running into some odd synthesis problems once trying to make a dual edged clock.

Also, it has been my experience to 'not' do a divided clock by using one of the bits, but rather to use it as an enable to drive something maintaining sync with the one and only true clock.

PROCESS abc (CLK, RESET) BEGIN

DIV_2_EN Completed process "Generate Post-Translate Simulation Model".

on

post

the

Reply to
K Mussatt

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.