Completed process "Generate Post-Translate Simulation Model".
ERROR: Hidden remap failed Reason:
Launching Application for process "Simulate Post-Translate VHDL Model".
not only the software's stupid enough to launch the GUI after the error, but there is not a single entry about this error in the xilinx database, on the modelsim server or even in google (but me complaining about the same problem a month ago) The 'reason' field is as useful as usual :) this time they just didn't bother typing a message that makes no sense, they just left it empty.
here's the code:
process(Reset, MasterClock) is variable counter : std_logic_vector(2 downto 0); begin if(Reset = '1') then counter := "000"; elsif(rising_edge(MasterClock)) then dividedclock