Hi - just finished reading this...
Does anybody think this affects the FPGAs with on-chip busses?
--neeraj
Hi - just finished reading this...
Does anybody think this affects the FPGAs with on-chip busses?
--neeraj
Ha flippin' ha. Here we go again.
Perhaps some of these turkeys should read the AMBA bus spec, or find out about what Inmos were doing and writing in the late 70s.
Not all prior art originates in the USA, despite what some USPTO patent examiners seem to think :-)
Just one delightful snippet from the "Background" section of this patent on the USPTO website:
Static timing analysis is preferably awkward, ...
Well, no; but patent lawyers, now, there's quite another thing.
Come on, the USPTO patent examiners wouldn't know prior art if it came up and bit them on the ass, mostly because the system largely relies on what the patent filer cites!
Which is, of course, a BIG &@#$2#$)(ing problem, as the inventor may lie, gloss over, or just through ignorance, neglect huge hunks of prior art.
And without a cost-effective way of interested third parties to attack the patent after being granted, one gets this huge minefield of garbage.
Yes big problem. An inventor should think "if my patent is worth anything someone will find all the prior art." There is a point after the patent is accepted and when it is issued that would be a good time for that some kind of public flogging of the patent.
Steve
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