We have an Infineon TC1100 processor connected to a 4Mx32 SDRAM (Micro Mt48LC4M32B2). Examining the memory signals with a logic analyser, the SDRAM is being correctly written, refreshed and read. However, although we can see the expected data being output on a read command, the data does not reach the processor.
The SDRAM setup code that we are using on our own board has been run on the TC1130 evaluation board where it works satisfactorily.
Apart from the setup of the EBU registers as described in Infineon's App Note 32113, are there any other registers that affect the delivery of bytes from the SDRAM to the LMB.
We have established by use of a logic analyser that we are able to configure the SDRAM controller to match the geometry of the SDRAM and correctly address banks, rows & columns, but I do take your point about the configuration table in the user manual.
Please consider the following, more detailed, description that I have posted on the "Yahoo TASKINGforum" news group.
We have a TC1100 processor connected to a Micron MT48LC4M32B2 SDRAM. The SDRAM has the following geometry :
4 Banks, 4096 rows(pages), 256 columns of 32bit words.
Using a logic analyser I can see data being written to the device and correctly read from the device, however the read data does not reach the LMB, that is it is neither visible to the Crossview debugger or to the test application that we are running.
The same SDRAM/EBU controler initialisation code has been run on a TC1130 TriBoard and apparently works; also the logic analyser traces from the TriBoard match our board.
We are using the following startup sequence :- EBU_CON = 0x0100000C0;
EBU_BUSCON0 = 0x30B20000; // SDRAM Type 0, // 32 Bit, // BC for SDRAM, // Always access device. EBU_ADDRSEL0 = 0xA8000031; // Address 0xA8000000 .. 0xA8FFFFFF, EBU_BUSAP0 = 0x00070000; // 7+1 cycles during burst access.
// Initialise the following for completeness. // Type 1 SDRAM not used. EBU_SDRMCON1 = 0x20031223; // Always page & Bank miss. EBU_SDRMOD1 = 0x00000023; EBU_SDRMREF1 = 0x00000049;
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