I have a problem synchronizing two AD9952 DDS chips. Both run from the same clock source (40MHz) and have the PLL multiplier at
10x. Both have the ClrAccumulator bit set, so when both DDS's are loaded with new frequency data (the same), a trigger on the IO_UPDATE signal (both connected together on a mpu IO pin), they are supposed to update the internal registers and at the same time clear the phase accumulator. Still, I have a phase difference between both DDS outputs which is, funny enough, 2 clock cycles (5ns), either leading or lagging or, coincidentally 0. I have done the same trick before with two AD9854, which didn't even have a ClrAccumulator feature, but resetting them once at the same time did the trick.
These AD9952's even have a master/slave mode which is supposed to keep them synchronised, but this doesn't work either. The PCB is laid out as 4 layer, power and ground in the middle, separate digital and analog supplies. All by the book, as as far as I know.
Funny thing is, and it might be a hint like a sledgehammer to others, is that when the slave DDS has it's sync output enabled, the phase difference is changing continuously while when this output is disable, it is contstant. So the whole problem might still be caused by some unwanted crosstalk on some signal trace.
Suggestions anyone?
Meindert