Hello,
There is a module provided online at Xilinx website for CLOCKGEN. In the EDK tools, when you perform synthesis it will create a top level VHDL code for the entire FPGA, that includes Microblaze, OPB, and your own design, etc. The clock going into this top level is the sys_clk, and this clock is going through a BUFG (inserted by EDK) and becomes sys_clk_s in the top level VHDL. The top level shows that this sys_clk_s is driving all the peripherals (i.e. Microblaze and OPB). In order to generate a clock for the external ZBT-memory, a "memory_27mhz" clock is generated by this CLOCKGEN module.
My questions are:
1) Should I drive this CLOCKGEN module using this "sys_clk_s"? Note: In order to get the EDK working, the IBUFG (MASTER_CLOCK) in the CLOCKGEN needs to be removed manually, because there is one inserted already by EDK as mentioned above.
2) If #1 is correct, then is the "clk_27mhz" after the DCM would be exactly the same as "sys_clk_s" that enters the CLOCKGEN?
3) In #2 is correct, is it okay to drive my own logic (not the Microblaze stuff or other peripherals) using the "clk_27mhz"?
You can reference page 18 of the MicroBlaze and Multimedia Development Board User Guide - there's a good diagram of the Clock Generator Module:
Any help is much appreciated! David