Hi all,
Is there a VHDL simulation model of the Spartan II/III boot process? I have some boot logic that runs in a CPLD and I'd like my testbench to have something that behaves like a booting FPGA.
-- Brad Eckert
Hi all,
Is there a VHDL simulation model of the Spartan II/III boot process? I have some boot logic that runs in a CPLD and I'd like my testbench to have something that behaves like a booting FPGA.
-- Brad Eckert
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