Stephen Williams wrote: ...
: Yes, the Verilog-2001 declaration assignment syntax works. For : example "reg foo = 1;" gets you a foo with an initial value of 1. : What's more, xst seems to know what to do with this as well. I : was at first reluctant to use it in my designs, doubting the xst : support, but I found it works, so I use it, now.
I know that option and use it. But even if I create a register with reg foo; XST gives that register a default value (FALSE). For the simulator however it is unknown (x). What I ask about is something like
pragma register_default_state FALSE
and then the simulator would come up with all registers in state FALSE if they are not initializes in an explicit way (either as above "reg foo = 1;" or in an initial statement)
: However, that really only simulates the power-on case. If you have : resets at times other then power on, or soft resets for subsystems, : this feature is obviously no help.