Xilinx ML310 board's IO

To those that are familiar with this board, I need about 50 or so digital io lines with a max bit rate of about 1Mb per second. I was considering using the PCI slot, but since I don't really want to build a full PCI compliant board, I was wondering whether if it is possible to comfigure as I want? Secondly are the data and address line directly connected to the FPGA, it seem to appear so the the block diagram but there seems to be a lot of passive components around the slots.

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Wing Wong.
Webpage: http://wing.ucc.asn.au
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Wing Fong Wong
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Why not use the the personality module connector? These are described in the user guides

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For example, PM2 (pg 65 of the users guide) has 39 LVDS pin pairs that can also be used as 78 single ended pins, so more than the 50 you are looking for.

The PCI is directly connected to the FPGA but the ALi south bridge, the PCI2PCI bridge, the Ethernet, and two PCI slots are sitting on that bus making it difficult to use for anything else than PCI.

- Peter

W> To those that are familiar with this board,

Reply to
Peter Ryser

And are the PM ports suited to low speeds( less than 1Mb per second)?

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Wing Wong.
Reply to
Wing Fong Wong

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