Hi, All:
I am quite new to ABEL HDL, I am debugging a digital design and come across following code.
...
IACK PIN 13;
INT5 NODE ISTYPE 'REG'; IVEC NODE;
EQUATIONS
INT5 := 0; INT5.LH = IVEC; INT5.RE = !IACK;
...
So, is INT5 a gated S-R Latch? if not, what is it? what will be the truth table? Seems to me INT5 will remain 0 forever.
Regards
Mark