116 warnings... successive approximation register using both phases of clock by spliting them

after compiling my project...116 warnings came ... i m new to VHDL.. gotta submit within 24 hrs HELP>>SOS>>SOS

hello thr

hi! i am stuck up pretty bad with my project and need your immediate assistance within 24hrs...... i have successive approximation register using VHDL and simulated it in Altera: Quartus 2 5.0 web edition.. now i have no errors but 116 warnings of all sorts plus output waveform is not what i was expecting either... now I tell you somethin regarding how it shud work and if you can please see what all you can do to make it run fine.... this is S.O.S.... save me man.......... I use a component called clock generator that provides me with two clocks both in phase opposition to each other (VHDL description is included in project).... so basically what i tried to do is to decrease the number of clock cycles tht normally takes for successive approximation by almost half.... from single clock I derived two clocks and divided the entire logic into two halves each running alternatively one after another so that by using both the halves of incoming clock I am able to get result in half the time... but anyways its all useless till the shit starts giving me correct outputs.... Well best of luck to you:

feel free for any other information......

VHDL code for clockgenerator is: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity clkgen is Port ( clk : in std_ulogic; nclk: out std_ulogic; pclk : out std_ulogic ); end clkgen;

architecture Behavioral of clkgen is begin nclk

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May I suggest to hire in emergency a consultant that you're gonna pay $$$$ to work out your problem thru the night.

Sylvain

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Sylvain Munaut

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