Fifo Block-RAM Xilinx ISE - port empty

Hello, I have generated a block-ram based FIFO queue (2 independent clocks, 2 inputs, 1 output) with the use of Core Generator. In the creator I used version without registered outputs (1 clock latency).

I tested it by this code:

process(P_I_CLK,P_I_RESET_N) variable v_state : integer := 0; variable licznikX : integer range 0 to 255 := 0;

begin if P_I_RESET_N = '0' then v_state :=0;

elsif P_I_CLK'event and P_I_CLK = '1' then sig_set_counter


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