Xilinx FPGA routing question


I have this question for a long time, just could not get an answer.

Assume we have a design consisting of several blocks and some of those blocks are hinhly regular (for example, a datapath). When we do P&R, does the tool take the advantage of this regularity and place those datapath element in series? Or it just does P&R globally without looking at the local regularity?

The reason I am asking this is that we have a design with blocks which are regular inside. But after P&R, the LUT utilization increases dramatically, it seems it uses lots LUT for routing which isn't expected just by looking at the regularity of the blocks.


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You may try to do some manual floor planning then let the router do the rest...

Don't expect the machine to understand everything you know...


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