Re: Nios Quartus II Question...

Ken,

This seems to be an evil of block-based schematic design. The more traditional blocks that we'd instantiate have a fixed set of ports... and no need to move connections around. For SOPC-type systems where peripherals and memory are added (or removed) with a mouse click, it becomes more difficult.

One trick I use is to highlight an area in the schematic file containing groups of pins & wires (connected to a block), and then cut & paste them to a blank area of schematic (for example the SDRAM pins as a group). Since the sets of IO for some piece of IP such as the SDRAM controller don't change, any update you do to a Nios/SOPC system will produce part of the schematic block with the exact same arrangement of IO ports... after modifying my system (and having the schematic block updated), I just select (as a group) the original IO pins, and drag them to connect up to the schematic block.

It seems though, that many folks are steering away from schematic blocks because of this in complex designs, in favor of hierarchic HDL. This approach can be taken for Nios designs as our top level (from SOPC Builder) is in fact an HDL file, but we provide schematic top-levels in our example designs for clarity & getting started purposes.

Jesse Kempa Altera Corp. jkempa at altera dot com

Jesse,

Thanks for the tips. Turning of rubberbanding is working like a charm.

Also, FYI, Altera online support verified the behavior and submitted an enhancement request.

I'm happy enough. Ken

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