Why is this group so quiet?

There is no such thing as a scaling "law". Different designs are different. That's why different chips from the same maker have different ratios... different target markets.

Not sure what your point is. This completely ignores the main issue which is designing the most useful FPGA for the cost. As devices have grown in size they found the routing was hogging too much real estate so they needed to push up from the bottom to eliminate the lowest level of interconnect. LUT6 based blocks get rid of a lot of low end routing in essence.

Remember, they sell you the routing and give you the logic for free.

I think this is a poor way of understanding what is needed in FPGAs. As devices grow, logic blocks grow. Consider the memory block, the multiplier/DSP block and now full fledged CPUs all "part" of the FPGA. This trend will continue with more and more built in functions being included as hard IP rather than soft IP using the FPGA fabric.

If we could get them to make FPGAs at the low end with better I/O capability (analog functions, clock oscillators, etc) such as is found in MCUs, they might just take out many of the general MCUs. How long can they continue to grow at the top end?

(snip, I wrote)

Different designs are different, but usually there is a trend.

There are, for example, scaling laws for MOS transistors, even though there are differences in the way individual ones are made.

If you make a log-log graph with the number of gates on one axis and number of FF on the other, you can see if there is a trend. Most often, there is.

Yes.

So, as you note, routing increases faster than logic as logic grows. There will be an exponent, likely between 1 and 2, that shows how it grows.

I suppose, but since different designs are different, it might need a few different types of chips. Some designs have no use for block RAM or multipliers, no matter how useful they are on average.

Could be interesting.

-- glen

I get what a trend is. I'm saying that the people from the FPGA companies have said there are wide variations based on the type of design being done. They shoot for the best compromise, but even that depends on a variety of factors. As I said before, even within one maker's lines, the ratio varies. So clearly there are different markets and not a one-size-fits-all.

And that is the sticky wicket! FPGA makers have resisted adding lots of hard IP (especially CPUs) because of the proliferation of combinations that ensue. With block memory and multipliers they generally picked a ratio to logic and worked with that. But even there, they have come out with lines with more or less of these relatively generic blocks depending on the applications. CPUs are a horse of another color. If you can work with off chip memory, that at least is out of the equation. Eventually there will be more and more hard IP used and FPGAs will proliferate the same way MCUs have. Or will it be that FPGA fabric will be added to CPUs and FPGAs will go the way of the PDA?

Needs to be economically "interesting" to the FPGA companies. Atmel had one at one time, but their technology was behind the power curve and they could never bring the cost down. Now Microsemi has a line of them with the same cost problem.

(snip)

To employ the language of a poet, that's metaphorically like an LDPC code. The group has a sparse error-correcting matrix (meaning a lot of circularly shifted answers that may sound alike), but with that it achieves the goal of rapid error-correction and error-detection capability in the low SNR region (meaning producing good and fruitful answers to all the poorly formulated questions and/or mistaken propositions)!

Evgeny.

Inspired answer! +1