hi there,
i have got a problem regarding simulation of my verilog source with gnu toolz.
the source file compiles properly with iverilog. but when i invoke the 'vvp', it dosn't output a 'vcd' file required for gtkwave.
i m running these gnu eda tools in native windows environment and not in linux/cygwin.
the commands that i give are -
iverilog -o my.vvp my.v vvp my.vvp -vcd
without any vcd file output. what can be the possible problem?
TIA Shreyas Kulkarni