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vvp problem

hi there,

i have got a problem regarding simulation of my verilog source with gnu toolz.

the source file compiles properly with iverilog. but when i invoke the 'vvp', it dosn't output a 'vcd' file required for gtkwave.

i m running these gnu eda tools in native windows environment and not in linux/cygwin.

the commands that i give are -

iverilog -o my.vvp my.v vvp my.vvp -vcd

without any vcd file output. what can be the possible problem?

TIA Shreyas Kulkarni

Reply to
Shreyas Kulkarni
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The -vcd argument to vvp merely sets the default dump format; you must enable VCD dumping in your HDL with something like

initial begin $dumpfile("foo.vcd"); $dumpvars(); #100000; $finish; end

Cheers, Peter Monta

Reply to
Peter Monta

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