i'am hunting this problem since a couple of days ... All I need is are 2 synchronous serial data-streams for my selfmade modulator. the clock phase must be in synch.
My idea was to use a master spi to generate the master stream and a spi slave module as second generator that is clocked by the clock out put from the first master.
For the first I use USART in master spi mode. for the second I tried the SPI module in slave mode and usart module in synchrounus slave mode. the first one fails because I can not put a second byte to the data register. It is not shifted out until the /SS is deactivated and activated again. Also because there is no double buffering there is virtually no time to update the data register. The second somehow fails. And I don't know why. when I try to send a0xAA pattern. sometimes there are two same bits following.
My system is XMega A1 running on 15MHz and the bit time is 2.5usec.
Anyone else having problems on this slave implementations?