I'm trying to use Virtex4 (Virtex4 LX25 Xilinx ML401 board) USER1 ~ USER4 JTAG commands from my software.
I have used my software to access such USER1, USER2 commands in previous generation FPGAs such as Virtex-II.
Virtex 4 uses different JTAG command bit patterns (10 bit long) and I changed the table so that JTAG commands to be issued have the correct JTAG command bit patterns.
Anyway, after spending hours and hours, I couldn't make it working. The JTAG command sequence seems correct as far as I see in the scope and HEX print out. Also, I can get the correct IDCODE using JTAG IDCODE command.
IDCODE = 10'b1111001001 USER1 = 10'b1111000010
I added probes to BSCAN module signals so that I could see the signals coming out from the BSCAN module. But I didn't see any signals coming out from the BSCAN module even I tried all USER1 ~ USER4 commands. (ex. sendIR(USER1) + readDR())
My question is "Does anybody try using the Virtex4 USERx JTAG command?"
If anybody have tried it, I definitely would like to hear that. I checked the Internet newsgroup as well as Xilinx support but so far, I cannot find any relevant info regarding to this.
Any info, any suggestions would be highly appreciated.
Best regards, Aki Niimura