Hi, is there any difference between Virtex-II and Virtex-4 5V tolerence? I did not find any information about that. I want to connect 5V outputs to Virtex-4 inputs. I read all the articles about 174ohm resistors and QuickSwitch. Does all that apply to Virtex-4, too? Regards Heiko
"Heiko Kalte" schrieb im Newsbeitrag news:db7djq$eb5$ snipped-for-privacy@enyo.uwa.edu.au...
you can assume pretty much the same applies, yes.
Antti
Yes, it does.
Austin
Let me put my tutorial hat on: Virtex-4 pins should not see a voltage significantly more positive than
4 V, because that would overstress the thin gate oxide in some transistors. As a means to avoid damage from electro-static discharge, there is a diode between each pin and its Vcc supply connection, preventing the pin from going more positive than Vcco + 0.7 V.If you drive the pin with a voltage >4 V, this diode gets forward-biased and will conduct tens of milliamps (provided Vcco is 3.3 V, which it should be if you want to be 5-V tolerant.) Now you need something to limit the current that the 5-V output drives into the protection diode, and through it into the 3.3-V supply. Limiting it to
Note that app. notes also specify, and this is important, that you power regulator must support inverse voltage
Imagine a case where your 3.3V network draw 50mA (for FPGA IO, 3.3
devices, ...). Then, the regulator that supply the 3.3V will outpu
50mANow, take a few IO that you put 5V on them, with resistors to limi
the current to 10mA. The way the FPGA is done, the IO pins hav protection diodes, which will take cut excess voltage at any IO t Vcco + 0.7V (diode at IO connected to the Vcc). Now, if you limi current to 10mA, with a resistor for example, the primary MO transistor at IO pin won't draw more current (still only some pico o nano-Amps). So, the 10mA that goes through the IO end-up feeding th
3.3V Vcco networkIn the case above, having only one IO feeded by 5V (with 10mA goin
through the IO), will feed the Vcco 10mA, while the regulator wil now only provide 40mA. You will still have 3.3V on Vcco. Th problem get if you feed more current than what is needed device connected to Vcco. If you get too much current through the IO, then the 3.3V regulator will no longer supply current. All the curren will come from the FPGA through the protection diodes. The very BA thing is that the Vcco line will no longer be regulated to 3.3V, bu will get up higher (4.3V or more)
So, you must ensure that the regulator can also sink excess current
to maintain the voltage to 3.3V
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