VHDL or Verilog?

Rick C. Hodgin · 2017-06-21T12:08:46+00:00

I've been given conflicting device on which language to use. There are people I would consider to be expert professionals who tell me to use VHDL, and others who tell me Verilog. Most everybody tells me that if I use VHDL there's less chance for error, but that it does take more effort to learn. Any thoughts? Thank you, Rick C. Hodgin

VHDL or Verilog?

Jun 21, 2017 20 Replies

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I'd be curious to see how it looks. I plan on mine being basically this simple:

Note: I have not listened to the audio on this video, but muted it and looked at the nodes illustration.

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I'll be sure to ask for helpers on the project. :-)

I know when I sit down to think things through, it goes so much more easily for me to think in concepts than in mechanics. I think the visual tool will allow me to both.

But, I have several steps ahead of Logician in line:

Visual FreePro, Jr. RDC and CAlive (compiler framework and C-like compiler) Visual FreePro (full version) ES/2 operating system (an open source OS/2 clone) Logician My various hardware designs

My long-term vision for completing these things are through

2025 if I can find revenue to allow me to devote my day labor hours to these projects, and some help. Otherwise, it will be a remainder-of-my-life kind of thing (I'm 47 now).

Thank you, Rick C. Hodgin