Implementing Bidirectional pins

Hi,

I'm trying to implement a bidirectional bus in my code. (VHDL, APEX20K1500E). But I'm having some trouble which brought me to ask the question :

How do I specify the direction signal while using a bidirectional bus ? I dont find myself setting any enable signals when using the bidirectional bus. I would appreciate it if someone could explain how this works.

Thanks, Prashant

Reply to
Prashant
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A bidirectional signal usually signifies read/write access to a resource (a memory location or a control register). If this is your application, the direction signal controls the enable signal of the bus drivers. In other words, when you read the data travels in one direction and when you write it travels the other direction. You set the enable signal correspondingly. As an example assume there is a driver which is active high for output enable from the memory to the outside, and there is an active high read, low write signal (rd_wrb). In this case, you'd connect the rd_wrb signal to the oe pin of the memory and when rd_wrb is one, data is driven from the memory to the bus and when rd_wrb is zero, memory uses the data on the bus.

Hope this helps,

Muzaffer Kal

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ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Reply to
Muzaffer Kal

Thanks Muzzafer,

So how does this work for pins on an FPGA ? I have specified some of the FPGA pins as bidirectional pins. I'm using the bidirectional pins to read from a register in the code or to write from a different register in the code. I dont understand how to specify the direction signal for the pins. I can do this at the signal/register level within the logic. But how are the bidirectional IO pins controlled ?

Thanks, Prashant

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Reply to
Prashant

I wont say I know the perfect way.. but typically you only have a bi-directional bus on the outside world. Inside the FPGA use an output bus and an input bus.

Xilinx have internal tristates but they can pig out on resources (I think) but other vendors don't so code portability will suffer if you use / rely on them.

tristate_bus : process (enable, dat_o) is begin if (enable = '0') then dat_bus 'Z'); else -- if enable = '1' dat_bus > >APEX20K1500E). But I'm having some trouble which brought me to ask the

implementations

Reply to
Simon Peacock

Suppose the following is your fpga top level:

module mydesign(rd_wrb, address, data); input rd_wrb; input [7:0] address; inout [7:0] data;

and this is your register block

reg [7:0] registers [7:0];

this is how you write to the memory

always @(rd_wrb or address or data) if (!rd_wrb) registers[address] = data;

and this is how you read from the registers including direction control

wire [7:0] data = rd_wrb ? registers[address] : 8'hZ;

this last line shows you control the direction signal for the pins. You take the input rd_wrb and connect it to the active high OE port of the data pins. Hope this help.

Muzaffer Kal

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ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Reply to
Muzaffer Kal

Hi Prashant, Try the following piece of code (taken from the VHDL template in the Quartus Text Editor, with a modification)

-- Quartus VHDL Template

-- Tri-State Buffer (Modified to make __tri_output_name a INOUT)

-- Replace the __variable_anme with your variable name

-- As the port direction is INOUT __tri_output_name can be used on the right

-- hand side of an assignment.

-- The __oe_input_name should be set to drive out to 0 so that __tri_output_name can then drive into the chip.

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY __entity_name IS

PORT ( __oe_input_name : IN STD_LOGIC; __data_input_name : IN STD_LOGIC; __tri_output_name : INOUT STD_LOGIC ); END __entity_name;

ARCHITECTURE a OF __entity_name IS BEGIN

PROCESS (__oe_input_name, __data_input_name) BEGIN IF __oe_input_name = '0' THEN __tri_output_name

Reply to
Subroto Datta

Hi Prashant, Try the following piece of code (taken from the VHDL template in the Quartus Text Editor, with a modification)

-- Quartus VHDL Template

-- Tri-State Buffer (Modified to make __tri_output_name a INOUT)

-- Replace the __variable_anme with your variable name

-- As the port direction is INOUT __tri_output_name can be used on the right

-- hand side of an assignment.

-- The __oe_input_name should be set to drive out to 0 so that __tri_output_name can then drive into the chip.

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY __entity_name IS

PORT ( __oe_input_name : IN STD_LOGIC; __data_input_name : IN STD_LOGIC; __tri_output_name : INOUT STD_LOGIC ); END __entity_name;

ARCHITECTURE a OF __entity_name IS BEGIN

PROCESS (__oe_input_name, __data_input_name) BEGIN IF __oe_input_name = '0' THEN __tri_output_name

Reply to
Subroto Datta

Hi prashant, All that you should know when the paricular pin is to act as input & when as output.The use a control signal like "oe" which i have in my following code .

Here "sda" is my bidirectional pin. Intenally I copy it to signal "out_sda" & use.While driving the pin "sda" i copy "int_sda" to "sda".this control is determined by the signal "oe".

process(oe,sda) begin if (oe = '1') then out_sda

Reply to
Raghavendra

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Hi,

I've also got a little problem with implemeting a bidirectional port on = a Spartan2.

When I use the following code:

process (ClkInt, ClkDir) begin =20 if ClkDir =3D '0' then SIGT

Reply to
HJO

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