When JTAG programming Xilinx FPGA, should other pins be constrained?

there is only one catch: JTAG is accessible and you can do boundary scan, etc when PROG is low, but programming over JTAG will fail. PROG needs a pullup in order to allow DONE go high

antti

Thanks for the tip.

This would suggest that PROG is being pulled low unintentionally.

I have no connections to this pin, which has a 4k7 pull-up on the FPGA board.

However, the symptoms are so similar that I think it is worth trying a stronger pull-up to see if that helps.

The 2k2 resistor in parallel with the 4k7 gives just under 1k5 pull-up.

Hurrah!

Seems to be working now.

Thanks again for your invaluable tip! :-)

K.

Kryten,

What chip?

Aust> The presence of the CPU in my project seems to prevent DONE going high.

Hi Austin,

at least with VirtexE there is no PROG pullup! or at least if the prog pin is floating then JTAG programming will yield in done not high error.

I just looked at S3 and S2 datasheets s3 says week pullup s2 schematic doesnt show pullup, but I would defenetly always design in and prog pin pullup as extra, correct me if I am wrong, maybe for some families it is ok to leave prog pin open

Antti

It is a XC2S300E.

Problem solved by decreasing pull-up resistor from 4k7 to 1k5.

Mind you, I would have thought 4k7 a medium strength pull-up. I tend to use 10k weakest, 1k strongest.

Check the start-up clock is selected for JTAG(bitstream options) is something to check. Also if you have access check what the INIT line does during the configuration. May be some clues there. Also like everyone else I recommend checking the values of pullup resistors.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.