Unused pins from FPGA to LAN91C111 (through NIOS)

Hi all,

I am interfacing LAN91C111 chip with NIOS II processor in an Altera Stratix device.

After I finish generating my system in SOPC Builder, I create the bdf file (or an hdl file) of the system in order to examine the INs and OUTs of the system. I observed that for lan91c111, the only outputs generated were IO RD and WR, ADS, WEN, BE, IRQ, Reset etc.

I checked the schematic of the NIOS Development Board (1S10ES), where there are many more signals going to lan91c111 chip from the FPGA (eg. CYCLE, LCLK etc.). However my NIOS design doesn't generate all the signals of the lan91c111 inputs. From where do I get these signals?

I noticed that whichever signal port was not generated in the bdf, should be high for asynchronous operation of the Ethernet. This is the case with NIOS development kit as well, in my opinion. Are these signals tristated from FPGA. In that case, can I do the same outside the FPGA chip using some high resistance (and hence save some of the FPGA pins) since I may never use sync mode of operation in my design.

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vizziee
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