I've run into an issue with the Bitgen software and Vref pins. In a design with a fairly high impedance Vref generator it is important that the Vref pins are floated in order to maintain the desired voltage.
I had a design where a national LP2995 termination voltage regulator had its Vref output pulled down almost to ground after configuration. I also noticed that it was being pulled up near 2.5V during configuration until I removed the pulldown resistor from the HSWAP_EN pin.
In this design, one bank had no input pins, so although the I/O for the bank was all SSTL_II_DCI, the Vref pins for that bank became "unused IOBs." Unused IOBs are pulled down by default in Bitgen. It was necessary to configure bitgen to float unused IOBs and handle any really unused pads by driving them explicitly in the design.
Other banks in the design worked correctly because they all contained a mix of inputs and outputs.