Hi, I am working on UART receiver. As of now, I am stucked at
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I could not find a proper hardware writing style to continue with line 14the overall hierarchy :
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module sampling_strobe_generator(clk, start_detected, sampling_strobe); // produces sampling signal for the incoming Rx
input clk, start_detected; output reg sampling_strobe = 0;
localparam CLOCKS_PER_BIT = 5000; // number of system clock in one UART bit, or equivalently 1/9600Hz divided by 1/48MHz
reg [($clog2(CLOCKS_PER_BIT)-1) : 0] counter = 0;
always @(posedge clk) begin if(start_detected) counter