Hi,
the data sheet tells 330MHz for CLKOUT_FREQ_2X_LF what yields into
ISE 6.2 compiles a small test with 200MHz clock (1x) constrains yielding into 800MBit/s. Will this work?
The device is a XC3S200-4FT256.
Thanks Thomas
Hi,
The 660 is feasible using a DCM. The 622 number in the data sheeet is more of a guideline. Most of the reasons that a design may not work at these high speeds are more to do with the package and pcb than the silicon. Beyond the 660 number, internal speed becomes the limiting factor, and the Virtex2 or Virtex4 becomes the best solution.
Cheers Nick
Thomas Rudloff wrote:
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