Hi all,
I'm working on a verification of a network on chip switch. FCII produces "latch inferred" warnings, and later we get "gated clock" warnings from Xilinx tools. When implemented in VirtexE, the switch (of course) has completely bogus output.
It was easy to identify a culprit: almost all the conditional assignments are incompletely specified.
Anyway, I'm having problems describing to the design team why their coding style is incomplete, especially because they claim that it works perfectly in a back-annotated simulation.
Could you please arm me with some examples of race_conditions/bugs that can emerge from those "latch inferred" warnings ?
Also, should I advise them to try simulating VHDL generated after routing in order to get more insight ?
Thx.
Best regards,