Latches inferred ?

Hi all,

I'm working on a verification of a network on chip switch. FCII produces "latch inferred" warnings, and later we get "gated clock" warnings from Xilinx tools. When implemented in VirtexE, the switch (of course) has completely bogus output.

It was easy to identify a culprit: almost all the conditional assignments are incompletely specified.

Anyway, I'm having problems describing to the design team why their coding style is incomplete, especially because they claim that it works perfectly in a back-annotated simulation.

Could you please arm me with some examples of race_conditions/bugs that can emerge from those "latch inferred" warnings ?

Also, should I advise them to try simulating VHDL generated after routing in order to get more insight ?

Thx.

Best regards,

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Domagoj Babic
domagoj (et) engineer.com
Reply to
Domagoj Babic
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Get them to simulate at the gate level and see if they get the same results. I'm guessing they won't ... that should be enough amo to shoot em down.

Mike

can

in

Reply to
Mike Lewis

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If your design team doesn't understand this I would be afraid, very afraid to place a design of any significance in their hands.

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Martin Euredjian
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Reply to
Martin Euredjian

I would also ask them to read very carefully the good white papers out of Xilinx and Altera that talk about efficient HDL coding styles for FPGAs. If you want performance, then coding for FPGAs is not the same as coding for ASICs. Gated clocks, latch inference, combinatorial feedbacks, product-term clocks etc are strict no-nos for FPGAs.

assignments

coding

perfectly

Reply to
Anil Khanna

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