Latches inferred ?

Question

Hi all,I'm working on a verification of a network on chip switch. FCII produces"latch inferred" warnings, and later we get "gated clock" warnings fromXilinx tools. When implemented in VirtexE, the switch (of course) hascompletely bogus output.It was easy to identify a culprit: almost all the conditional assignmentsare incompletely specified.Anyway, I'm having problems describing to the design team why their codingstyle is incomplete, especially because they claim that it works perfectlyin a back-annotated simulation.Could you please arm me with some examples of race_conditions/bugs that canemerge from those "latch inferred" warnings ?Also, should I advise them to try simulating VHDL generated after routing inorder to get more insight ?Thx.Best regards,--Domagoj Babicdomagoj (et)

Mike Lewis · Accepted Answer

Get them to simulate at the gate level and see if they get thesame results. I'm guessing they won't ... that should beenough amo to shoot em down.Mikecanin

Martin Euredjian · Answer

...If your design team doesn't understand this I would be afraid, very afraidto place a design of any significance in their hands.-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Martin EuredjianTo send private email:where"0_0_0_0_"  =  "martineu"

Anil Khanna · Answer

I would also ask them to read very carefully the good white papers out of Xilinx and Altera that talk about efficient HDL coding styles for FPGAs. If you want performance, then coding for FPGAs is not the same as coding for ASICs. Gated clocks, latch inference, combinatorial feedbacks, product-term clocks etc are strict no-nos for FPGAs.

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Latches inferred ?

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