Races in Verilog can also be avoided by following a coding standard. I agree they are easier to make, though.
I have never been bitten by a race in Verilog, whereas I have been bitten by races in VHDL on several occasions! This has always in other people's code though. This may be a reflection of the relative amount of time I've spent with the two languages, rather than any property of the languages themselves.
I didn't think the VHDL LRM defined the order in which processes are executed. Can you point to the particular part of the LRM that says this? Without a defined order, different simulators may produce different results.
Yes, I have seen differences between VHDL simulators that weren't considered to be bugs (Simili vs Modelsim, using the delta delayed clock example from an earlier post).
I disagree with the "forget about it" part. Races in VHDL do cause problems in real-world designs. I have seen plenty of examples (including a broken ASIC). This seems to be more of a problem in testbenches, because designers typically don't introduce delta delays to clocks in synthesisable code.
Regards, Allan.