Substitute for FORK / JOIN?

Jun 23, 2007 2 Replies

Hi guys:



I'm writing a program in Verilog where I need for several blocks of code to execute concurrently (parallel blocks). I used the "fork - join" command which should do just what I want. Unfortunately, my Xilinx Spartan-3 does not support this command.



Is there another way to get parallel blocks in Verilog?



Thanks for any replies.



Don



Each "always" block executes in parallel with every other "always" block. That's how you model concurrency in hardware - each "always" block typically represents an independent piece of hardware, busily and continually doing its own thing.

fork...join is occasionally handy for modelling certain kinds of concurrent activity in simulation, but is never synthesisable. What are you trying to do? It sounds suspiciously as though you are trying to map a software view of the world on to hardware, without having a clear picture of the underlying hardware architecture that you want to implement.

Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.

Only in simulation,but not in real hardware

No hardware will support the fork - join command, because it is not synthesizable.

As bromley suggested, all the lines in a synthesizabele code will run in parallel based on the events. So you need to just separete operations into different always blocks based on some events. Or you can separate that into different modules if you feel so. Eg: if you want type A and type B operation to be performed on the 'data' and get the output1 and output2. create something like this (dont look at the syntax). module typeA (data,control1,output1); module typeA (data,control2,output2); Two operations will proceed in parallel depending on the control1 and control2. any way you first correctly understand the difference between the software and the Hardware very clearly. When writing a synthesizable verilog code always you should have a clear picture of the underlying hardware. regards Sumesh V S

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