Strange FPGA problem

Apr 19, 2005 3 Replies
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Hello,



I am integrating an IP core and i am facing a strange problem. One of the register of the IP core which is R/W register is not writable ..in simulation I am able to write but when ported to FPGA I am not able to write?its default value is also wrong and when I write to one fixed register in that core... its value gets reflects on that register. Reset value of all the register is ok and I am able to read and write all R/W registers except one. What may be the problem?..since simulation results shows that the IP is ok?so I cannot pin point that tell the IP vendor that there is a bug in ur IP?..



Any feedback??? Thanks and Regards Williams


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E

Sometimes a register in a register file has a constant value. E.g. R0 in the MIPS is always 0.

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Maybe you have a similar problem (hence your IP model is incorrect)

Egbert Molenkamp

"williams" schreef in bericht news: snipped-for-privacy@posting.google.com...

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Hi Williams:

If you are using Verilog: Check your port-width mismatches in the instantiation(s)/wire(s)/reg(s) definitions. Even if verilog, does not report above errors, go through the synthesis report warnings in detail.

-Navneet

williams wrote:

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Just a hunch, but this smells like a bitstream loading problem. Perhaps your connection while loading the bitstream was not OK. Try reloading the bitstream and check after that.

- Swapnajit.

-- SystemVerilog, DPI, Verilog PLI and all other good stuffs. Project VeriPage:

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