Hi,
As I have asked in a previous post without any answer I ask it again : what is the relationship if any between SSO and the proper decoupling of an FPGA ? It seems there is one because the xilinx datasheet (the one I read) indicate a maximum sso provided decoupling is perfect.
Best regards,
JF
JF -
From what I've read, board-level decoupling has a 2nd-order effect on controlling SSO noise. The problem really needs to be tackled inside the FPGA package, which is mostly out of your control. Use a device in a flip-chip package if you can. That said, proper board-level decoupling does help (follow Xilinx's guidelines), and there are other things you can do. For example, picking pin assignments to spread the drivers out on the package (you can control this unless the board has already been fabbed). And use the slowest drivers possible (not always an option). The board stackup and how the signals are routed are also important.
As for the specific impact of decoupling and SSO noise, decoupling reduces the AC impedance (inductance dominates) between voltage and GND planes. Switching currents flow in a loop, and the lower the loop inductance the fewer SSO problems you'll have.
Big topic, but there's a lot of information out there. Good luck.
RJS
what
FPGA
SSO stands for "simultaneously switching outputs", previously also referred to as "ground bounce", and describes the effect of output switching on the chip-internal ground and Vcc distribution. Switching many outputs simultaneously generates fairly large current changes in the inductnce between the chip ground and the system ground plane, or between the chip Vcc and the Vcc poard plane. Good decoupling makes the board-Vcc distribution "stiffer", and thus makes SSO more deterministic, although not necessarily better. Peter Alfke
JF
(aside: why is it that all hypenated French names are now just two letters? A result of Dallas (the old TV show)?"
Ground bounce is from the series inductance in the pcb, package, etc.
V=-L dI/dt
There is no "C" in the equation (capactance).
Please refer to out power app notes, and:
(sorry for the long URL)
Bypassing is another issue altogether. The two are related, as a poor choice of bypass capacitors can create resonance effects with the series inductance.
Aust> Hi,
One board level design technique for reducing adverse effects of SSO is what Xilinx refers to as "virtual GND/VCC". That is driving spare outputs with 0 and tieing to GND plane, or 1 and tieing to VCC plane.
Check answer record 12692 at Xilinx site.
-- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. Colorado based Xilinx consultant
email : snipped-for-privacy@rtc-inc.com web :
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