Maximum allowable ground bounce for xilinx fpgas


I read in a previous post the following by M. Lesea :

"All design (SSO tables, DCM operation, system jitter, etc) assumes that the ground bounce stays below +/- 100 mV peak to peak for proper operation."

Where is this information located in the datasheet ?



Reply to
jean-francois hasson
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It is not in the datasheet.

I was stating what our internal design guidelines are for simulating the performance of our circuits when exposed to the real noise that is likely to be present.

Information like this is presented in the power distribution system design applications notes, however.

Ca va?


jean-francois hass> Hi,

Reply to
Austin Lesea

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