SSO and other banks behavior of Xilinx FPGAs

Hi,

I have read a few articles about SSO and the fact that ground bounce may occur and therefore the ground reference of the chip is different from the ground of the board the chip is on. I was wondering if a ground bounce problem on one bank of an FPGA could create issues on other interfaces located on other banks of the FPGA ? I also understood that SSO guidelines for Xilinx FPGAs were given considering a perfect decoupling system. What is the impact of decoupling on the fact that many outputs switch at the same time and that the return current is too important on one ground pin involving ground bounce ?

Thanks,

JF