How important is the trace length balance on signal lines to SDRAM? I recall coming across a document saying that the trace lengths needed to have less than .5 inch difference from shortest to longest. But I think that was a DDR2 doc.
I see some very obvious S curves in the lines on an Atmel SAM9261 EK board that uses PC100 speed SDRAMS. We will be using similar parts on a new design. Someone else I have been chatting with says not to worry about it.
It doesn't seem to be a very straight forward thing to do, although possibly some pcb layout software can do this automatically.
Does anyone have strong support for using or not using length balancing? If it's important, processor is the SAM9261 and there will be two 16 bit SRAMS (for 32 bit wide data path) and 1 16bit Flash.