Read/Write data from/to SRAM

Have a closer look at the control signals OE_N, WE_N, CS_N. Is the sram address stable before these signals are asserted for write cycle?

Rgds

Oscar, with that level of detail (= lack thereof) we can't help much.

In my SRAM controller (Cyclone hooked up to two IDT71V416) I take four (10ns) cycles for write:

- one to turn of the output enable (OE_N = 0),

- one to load the address and data, and open the output drivers,

- one to write the data (WE_N = 1)

- one to turn it back off (WE_N = 0)

For writes after write in a row, the first cycle can be shaved off, but I haven't been able to bring the write process down under three cycles in spite of the datasheet's claimed 0 tWR. I don't know if that's normal (this is with the Nios development board, Cyclone edition).

I'm more concerned about the maximum read performance. Reading the data sheet, the positive (4 ns) tOH made me think that I could sustain a read every cycle (the tRC is 10ns as is my cycle time), but my testing has given inconsistent results.

Question to the experts: Is this (simplified example) safe?

assign fse_a = read_addr; always @(posedge clk) begin read_data