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DS1210 NVram Controller Puzzle

I am looking for some historical information regarding this component. The DS1210 has been around for some time (around '90, I think) and was first made by Dallas Semi before being acquired by Maxim Semi.

Tektronix designed one of these parts (around '90 or so) in one of their spectrum analyzers to back up some SRAM parts. I have posted a snippet of their circuit (as well as a datasheet) at:

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There are two questions that I have:

1) Why did they wrap a diode around from the Bat to the Vcco output? The part is suppose to provide this function internally. Was there a problem with the earlier versions of the part that required this extra insurance?

2) Tek uses the CEO! to prevent unintended corruption to the NVRAM by qualifying this signal with the SRAM CS lines. The snippet shows the CE! line at a hard low. The thought is that when the Vcc line drops to < 4.75V, the CEO! will pull high preventing accidental writes. However, if you look at the current datasheet (sht 2 highlighted) Maxim states that when the DS1210 detects the out of tolerance Vcc AND should the the CE! line happen to be low (reading/writing), then the CEO! line will remain low until the completion of the read/write cycle. Since the CE! is at a hard low, I would think that the CEO! would never go high in this instance. Unfortunately, the timing diagrams do not seem to show this scenario.

The main question is was the DS1210 in the 90's the same functionally as the one that is currently available. I searched for errata sheets on the Maxim website and couldn't find anything. Wished I could find a detailed block diagram that might shed some light.

Looking for opinions - Thanks! Jim

Reply to
Jim Flanagan
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Is the battery is rechargeable or lithium type?

Some of the 8K RAM chips at the time had two chip selects.

What is the part number of the chip used there ??

don

Reply to
don

I don't remember that particular part, but I do remember an event, around 1980, with NCR.

Their cash registers used NVRAM to back-up transactions in case of power-failure or main computer system drop-out.

They were having issues with incoming inspection testing of NVRAM parts.

So (at GenRad Portable Testers Division) I designed and built a one-off NVRAM tester.

Off to Dayton it went.

A week later got a call, "Your tester doesn't work, _everything fails."

Had their engineer bring back the tester with some parts.

My tester was PERFECT!

ALL their parts were BAD ;-) ...Jim Thompson

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Reply to
Jim Thompson

Didn?t they have a write sequence 0x55 0x55 0xAA 0xAA 0x55 in that series to initiate a write? I think I had used a 1213 or something similar to the 1210. Big chip with every thing in the package. Worked like a charm

Cheers

Reply to
Martin Riddle

Interesting that they tied CE to ground, and that they added a diode.

I've made my own equivalent battery-backed ram interface with a diode and an HC logic gate, with the gate itself powered by the battery. Seems to work.

Flash chips do that. The part in question is a battery-backed SRAM.

I've used some of the potted-brick ST battery-backed SRAMs to replace old Dallas things in Tek sampling scopes. They plug right in. The Dallas socket adapters tend to fail in very roughly 15 years.

We use Panasonic coin-cell lithiums to back up an MC68332 uP RAM in some of our products. Sometimes we get back an old repair unit and pull the battery and measure remaining capacity. Over about a 12 year timebase, we see no obvious discharge trend at all. In fact, the batteries with the most available mAh tend to be the older ones.

John

Reply to
John Larkin

The only conclusion I can come to is that CEO! will only remain low when a power fail is detected *iff* a falling edge on CE! has been detected whilst it was in the powered up state and CE! is still low, and will remain low until CE! goes high. Ohterwise CEO! goes high immediately whenever Vcc is below the fail threshold. Normally CEO! follows the state of CE! when in the powered up state, so CEO! will go low again once power is re-applied if CE! is strapped to ground. Since there are no falling edges on CE! while powered up the stretching circuit doesn't kick in.

Evidence that some kind of falling edge detection is already used internally is when they talk about inhibiting the second cycle when detecting low battery, they must be counting cycles somehow, probably using falling edges on CE!.

This would also explain the operation of the processor reset app circuit in the datasheet that does just this, i.e. tie CE! low.

As for the diode, the chip is supposed to switch Vcco to whichever is the highest of Vcc, Vbat1 or Vbat2. It would seem this diode is belt and braces and not necessary.

Mark. .

Reply to
markp

The diode is not a normal schottly diode, but a current regulating diode with very low forward voltage at low currents. I think what they are doing is providing a lower voltage dropout than the DS1210 thereby increasing their battery life. It has to be a diode in behaviour because Vcco is switched to the highest of Vcc and Vbat.

Reply to
markp

Mark - I appreciate your comments. After I made the post, further research showed that if the CE! line is tied low, then on power up there is a finite delay (they never spec'd how much delay) before the CEO! line goes high. So it will go high, as you said, on power up, but there is a delay which

*could* cause a potential corruption scenario. Therefore, Maxim warns NOT to do implement the part in this manner. The information was tucked away in an application note. Seems that this information should have made it into the datasheet after all these years.

Thanks again and take care - Jim

Reply to
Jim Flanagan

I've just looked at that app note

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The assumption on my part, and as stated in the datasheet, was that the CEO! is driven high at the power fail threshold. It seems that this is actually done at the point where the battery is switched in, which happens when Vcc becomes lower than Vbat. As retention supply is generally less than active supply voltage for non volatile devices you get into a potential corruption problem. This looks like a design error, CEO! should always be protected at the point of power fail detect, not at the point where the battery is switched in :-o

Mark.

Reply to
markp

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